1. Field of the Invention
The present invention relates to a level shifter for simultaneously generating complementary outputs at “H” level or “L” level, and a signal generator circuit suitable for controlling the level shifter.
2. Description of the Related Art
Conventionally, there have existed several level shifters for simultaneously generating complementary outputs at “H” level or “L” level, for example, a first level shifter 10 shown in FIG. 1, a second level shifter 20 shown in FIG. 2, and the like. These level shifters are combined with a signal generator circuit 5 shown in FIG. 3, and receive part of signals outputted from the signal generator circuit 5 as control signals.
In the following, the signal generator circuit 5 will be first described with reference to FIGS. 3 and 4, the first level shifter 10 and second level shifter 20 will be next described with reference to FIGS. 1 and 2, and a first level shifter 100 which incorporates the signal generator circuit 5 described with reference to FIG. 3 (hereinafter called the “level shifter 100 having a signal generator circuit), and a second level shifter 200 which incorporates the signal generator circuit 5 described with reference to FIG. 4 (hereinafter called the “level shifter 200 having a signal generator circuit) will be finally described.
First, the signal generator circuit 5 will be described. FIG. 3 shows the configuration of the conventional signal generator circuit.
As shown in FIG. 3, the signal generator circuit 5 comprises an input terminal 11 for receiving an input signal IN01; an output terminal 12 for outputting a first output signal OUT01; an output terminal 13 for outputting a second output terminal OUT02; an output terminal 14 for outputting a third output signal OUT03; and an output terminal 15 for outputting a fourth output signal OUT04.
The signal generator circuit 5 also comprises an inverter INV; a first low voltage inverter INVL1; and a second low voltage inverter INVL2. These components form a low voltage signal generator unit for generating a signal at a low voltage level.
The low voltage generator unit is configured in the following manner. Specifically, the input signal IN01 applied from the input terminal 11 is inverted by the inverter INV, and branched into three. One of the three branched signals is outputted to the input side of the first low voltage inverter INVL1; one is outputted to the input side of the second low voltage inverter INVL2; and one is outputted to the outside from the output terminal 13 as the second output signal OUT02.
The low voltage signal generator unit is used for adjusting the output of a level shifter (first level shifter 10, second level shifter 20, and the like) combined therewith. Therefore, the low voltage signal generator unit may be in some cases called an “output adjustor circuit unit.”
The signal generator circuit 5 also comprises a high voltage power supply VDDH, and a ground potential VSSH. “VSS” in the ground potential VSSH represents “ground,” and H represents a high voltage output system. Disposed between the high voltage power supply VDDH and ground potential VSSH are a circuit comprised of a high voltage P-ch transistor P1, a high voltage inverter INVH1, the aforementioned first output terminal 14, and a high voltage N-ch transistor N1; and a circuit comprised of a high voltage P-ch transistor P2, a high voltage inverter INVH2, the aforementioned second output terminal 15, and a high voltage N-ch transistor N2. These circuits form a level shifter unit for generating a high voltage level signal.
The level shifter unit is configured in the following manner. Specifically, the high voltage P-ch transistors P1, P2 have their sources commonly connected to the high voltage power supply VDDH. Also, the high voltage P-ch transistor P1 has a gate branched for connection to a line which connects a drain of the high voltage P-ch transistor P2 with a drain of the high voltage N-ch transistor N2; and a drain connected to a drain of the high voltage N-ch transistor N1. The high voltage P-ch transistor P2 has a gate branched for connection to a line which connects the drain of the high voltage P-ch transistor P1 with the drain of the high voltage N-ch transistor N1; and the drain connected to the drain of the high voltage N-ch transistor N2. The high voltage P-ch transistors P1, P2 form a flip-flop circuit through the foregoing connections. The high voltage N-ch transistor N1 in turn has a source connected to the ground potential VSSH; a gate branched for connection to a line which connects the output side of the inverter INV with the input side of the first low voltage inverter INVL1; and a drain connected to the drain of the high voltage P-ch transistor P1. The high voltage N-ch transistor N2 has a source connected to the ground potential VSSH; a gate connected to the output side of the first low voltage inverter INLV1; and a drain connected to the drain of the high voltage P-ch transistor P2. The output terminal 14 for outputting the third output signal OUT03 is branched for connection to a line which connects the drain of the high voltage P-ch transistor P1 with the drain of the high voltage N-ch transistor N1 through the high voltage inverter INVH1. The output terminal 15 for outputting the fourth output signal OUT04 is branched for connection to a line which connects the drain of the high voltage P-ch transistor P2 with the drain of the high voltage N-ch transistor N2 through the high voltage inverter INVH2.
The low voltage signal generator unit generates a low voltage level signal, whereas the level shifter unit generates a high voltage level signal. Therefore, in the following, the low voltage signal generator unit may be in some cases called a “low voltage output section” and the level shifter unit a “high voltage output section.”
FIG. 4 is a timing chart showing the operation of the conventional signal generator circuit. The signal generator circuit 5 outputs each output signal at a timing as shown in FIG. 4.
Next, the first level shifter 10 will be described. FIG. 1 is a diagram showing the configuration of the first level shifter.
As shown in FIG. 1, the first level shifter 10 comprises an input terminal 111 for receiving a first input signal IN11 for the first level shifter 10; an input terminal 112 for receiving a second input signal IN12; an input terminal 113 for receiving a third input signal IN13; an output terminal 114 for outputting a first amplified output signal OUT11; and an output terminal 115 for outputting a second amplified output signal OUT12.
The first level shifter 10 also comprises a first low voltage NAND element NADL11 and a second low voltage NAND element NANDL12 (hereinafter called the “first NAND L11” and “second NAND L12,” respectively). The first NAND L11 has one input side connected to the input terminal 111 for receiving the first input signal IN11, and the other input side branched for connection to a line which connects the input terminal 112 for receiving the second input signal IN12 with the input side of the second NAND L12. The second NAND L12 has one input side connected to the output side of the NAND L11, and the other input side connected to the input terminal 112 for receiving the second input signal IN12.
The second output signal OUT02 of the signal generator circuit 5 shown in FIG. 3 is applied from the input terminal 112 as the second input signal IN12 of the first level shifter 10. Also, the third output signal OUT03 of the signal generator circuit 5 shown in FIG. 3 is applied from the input terminal 113 as the third input signal IN13 of the first level shifter 10.
The first level shifter 10 also comprises a high voltage power supply Vpp and a ground potential VSSH. Disposed between the high voltage power supply Vpp and ground potential VSSH are a circuit comprised of high voltage P-ch transistors P11–P12, a high voltage inverter INVH11, the aforementioned first output terminal 114, and a high voltage N-ch transistor N11; and a circuit comprised of high voltage P-ch transistors P13–P14, a high voltage inverter INVH12, the aforementioned second output terminal 115, and a high voltage N-ch transistor N12.
These circuits are configured in the following manner. Specifically, the high voltage P-ch transistors P11, P13 have their sources commonly connected to the high voltage power supply Vpp, and their gates connected to the input terminal 113 for receiving the third input signal IN13. The high voltage P-ch transistor P11 has a drain connected to a source of the high voltage P-ch transistor P12, while the high voltage P-ch transistor P13 has a drain connected to a source of the high voltage P-ch transistor P14. The high voltage P-ch transistor P12 also has the source connected to the drain of the high voltage P-ch transistor P1, a gate branched for connection to a line which connects the drain of the high voltage P-ch transistor P14 with a drain of the high voltage N-ch transistor N12, and a drain connected to a drain of the high voltage N-ch transistor N11. The high voltage P-ch transistor P14 has a source connected to the drain of the high voltage P-ch transistor P13, a gate branched for connection to a line which connects the drain of the high voltage P-ch transistor P12 with the drain of the high voltage N-ch transistor N11, and a drain connected to the drain of the high voltage N-ch transistor N12. The high voltage P-ch transistors P12, P14 form a flip-flop circuit through the foregoing connections. The high voltage N-ch transistor N11 has the source connected to the ground potential VSSH, the gate branched for connection to a line which connects the output side of the first NAND L11 with one input side of the second NAND L12, and the drain connected to the drain of the high voltage P-ch transistor P12. The high voltage N-ch transistor N12 has a source connected to the ground potential VSSH, a gate connected to the output side of the second NAND L12, and a drain connected to the drain of the high voltage P-ch transistor P14. The output terminal 114 for outputting a first amplified output signal OUT11 is branched for connection to a line which connects the drain of the high voltage P-ch transistor P12 with the drain of the high voltage N-ch transistor N11 through the high voltage inverter INVH11. The output terminal 115 for outputting a second amplified output signal OUT12 is branched for connection to a line which connects the drain of the high voltage P-ch transistor P14 with the drain of the high voltage N-ch transistor N12 through the high voltage inverter INVH12.
Next, the second level shifter 20 will be described. FIG. 2 is a diagram showing the configuration of the second level shifter.
As shown in FIG. 2, the second level shifter 20 comprises an input terminal 211 for receiving a first input signal IN11 for the second level shifter 20; an input terminal 212 for receiving a second input signal IN12′; an input terminal 213 for receiving a third input signal IN13′; an output terminal 214 for outputting the first amplified output signal OUT11; and an output terminal 215 for outputting the second amplified output signal OUT12.
The second level shifter 20 also comprises a first low voltage NOR element NOR L21 and a second low voltage NOR-element NOR L22 (hereinafter called the “first NOR L21” and “second NOR L22,” respectively). The first NOR L21 has one input side connected to the input terminal 211 for receiving the first input signal IN11, and the other input side branched for connection to a line which connects the input terminal 212 for receiving the second input signal IN12′ with the input side of the second NOR L22. The second NOR L22 has one input side connected to the output side of the NOR L21, and the other input side connected to the input terminal 212 for receiving the input signal IN12′.
The first output signal OUT01 of the signal generator circuit 5 shown in FIG. 3 is applied from the input terminal 212 as the second input signal IN12′ of the second level shifter 20. Also, the output signal OUT04 of the signal generator circuit 5 shown in FIG. 3 is applied from the input terminal 213 as the third input signal IN13′ of the second level shifter 20.
The second level shifter 20 also comprises a high voltage power supply Vpp and a ground potential VSSH. Disposed between the high voltage power supply Vpp and ground potential VSSH are a circuit comprised of high voltage P-ch transistors P21-P22, a high voltage inverter INVH21, the aforementioned first output terminal 214, and a high voltage N-ch transistor N21; and a circuit comprised of high voltage P-ch transistors P23—P23, a high voltage inverter INVH22, the aforementioned second output terminal 215, and a high voltage N-ch transistor N22.
These circuits are configured in the following manner. Specifically, the high voltage P-ch transistors P21–P24 have their sources commonly connected to the high voltage power supply Vpp. The high voltage P-ch transistor P21 has the source connected to the high voltage power supply Vpp, a gate connected to the input terminal 213 for receiving the third input signal IN13′, and a drain branched for connection to a line which connects a drain of the high voltage P-ch transistor P22 with a drain of the high voltage P-ch transistor N21. The high voltage P-ch transistor P22 has the source connected to the high voltage power supply Vpp, a gate branched for connection to a line which connects a drain of the high voltage P-ch transistor P23 with a drain of the high voltage N-ch transistor N22, and a drain connected to the drain of the high voltage N-ch transistor N21. The high voltage P-ch transistor P22 has the source connected to the high voltage power supply Vpp, a gate branched for connection to a line which connects the drain of the high voltage P-ch transistor P22 with the drain of the high voltage N-ch transistor N21, and a drain connected to the drain of the high voltage N-ch transistor N22. The high voltage P-ch transistor P23 has the source connected to the high voltage power supply Vpp, a gate branched for connection to a line which connects the drain of the high voltage P-ch transistor P22 with the drain of the high voltage N-ch transistor N21, and a drain connected to the drain of the high voltage N-ch transistor N22. The high voltage P-ch transistor P24 has the source connected to the high voltage power supply Vpp, a gate connected to the input terminal 213 for receiving the input signal IN13′, and a drain branched for connection to a line which connects the drain of the high voltage P-ch transistor P23 with the drain of the high voltage P-ch transistor P22. The high voltage P-ch transistor P22 and high voltage P-ch transistor P23 form a flip-flop circuit through the foregoing connections. The high voltage N-ch transistor N21 has a source connected to the ground potential VSSH, a gate branched for connection to a line which connects the output side of the first NOR L21 with one input side of the second NOR L22, and a drain branched for connection to a line which connects the drain of the high voltage P-ch transistor P21 with the drain of P22. The high voltage N-ch transistor N22 has a source connected to the ground potential VSSH, a gate connected to the output side of the second NOR L22, and a drain branched for connection to a line which connects the drain of the high voltage P-ch transistor P23 with the drain of P24. The output terminal 214 for outputting a first amplified output signal OUT11 is branched for connection to a line which connects the drain of the high voltage P-ch transistor P22 with the drain of the high voltage N-ch transistor N21 through the high voltage inverter INVH21. The output terminal 215 for outputting a second amplified output signal OUT12 is branched for connection to a line which connects the drain of the high voltage P-ch transistor P23 with the drain of the high voltage N-ch transistor N22 through the high voltage inverter INVH22.
Next, the level shifter 100 having a signal generator circuit will be described. FIG. 5 is a diagram showing the configuration of the conventional level shifter having a signal generator circuit.
As shown in FIG. 5, the level shifter 100 having a signal generator circuit is a combination of the signal generator circuit 5 with the first level shifter 10, which is made such that the second output signal OUT02 of the signal generator circuit 5 shown in FIG. 3 serves as the second input signal IN12 of the first level shifter 12 shown in FIG. 15, and the third output signal OUT03 of the signal generator circuit 5 shown in FIG. 3 serves as the third input signal IN13 of the first level shifter 10 shown in FIG. 1.
Next, the level shifter 200 having a signal generator circuit will be described. FIG. 6 is a diagram showing the configuration of the conventional level shifter having a signal generator circuit.
As shown in FIG. 6, the level shifter 200 having a signal generator circuit is a combination of the signal generator circuit 5 with the second level shifter 20, which is made such that the first output signal OUT01 of the signal generator circuit 5 shown in FIG. 3 serves as the second input signal IN12′ of the second level shifter 20 shown in FIG. 2, and the fourth output signal OUT04 of the signal generator circuit 5 shown in FIG. 3 serves as the third input signal IN13′ of the second level shifter 20 shown in FIG. 2.
The level shifters 100, 200 having a signal generator circuit shown in FIGS. 5 and 6, and the like simultaneously generate complementary outputs at “H” level or “L” level.
Such a signal generator circuit and a level shifter having a signal generator circuit are disclosed, for example, in Laid-open Japanese Patent Application No. 4-223713 (Patent Document 1).
The conventional level shifters 100, 200 having a signal generator circuit have a problem that a through current may flow between the high voltage power supply Vpp and the ground potential VSSH.
This problem occurs in the following manner. Specifically, the conventional level shifters 100, 200 having a signal generator circuit employ the output signals of the signal generator circuit 5 as a control signal for a high voltage level and as a control signal for a low voltage level without adjusting their timings. However, the conventional signal generator circuit 5 may experience a shift of a timing at which an output signal at high voltage level changes from a timing at which an output at low voltage level changes due to the characteristics of the high voltage elements and low voltage elements. Particularly, when the timing at which the output signal at high voltage level changes overlaps with the timing at which the output signal at low voltage level changes in the signal generator circuit 5, a through current flows between the high voltage power supply Vpp and the ground potential VSSH of the conventional level shifters 100, 200 having a signal generator circuit.
For example, in the level shifter 100 having a signal generator circuit shown in FIG. 5, the third input signal IN13, which is a control signal for the high voltage level (i.e., the third output signal OUT03 of the signal generator circuit 5), changing from “L” level to “H” level, and the second input signal IN12, which is a control signal for the low voltage level (i.e., the second output signal OUT02 of the signal generator circuit 5), changing from “H” level” to “L” level cause both the amplified output signals OUT11, OUT 12 to transition to the high voltage “H” level. However, if the second input signal IN12 transitions to “L” level before the third input signal IN13 transitions to “H” level, a through current flows between the high voltage power supply Vpp and the ground potential VSSH through the high voltage P-ch transistors P11, P12 and high voltage N-ch transistor N11 or through the high voltage P-ch transistors P13, P14 and high voltage N-ch transistor N12.
On the other hand, in the level shifter 200 having a signal generator circuit shown in FIG. 6, the second input signal IN12′, which is a control signal for the low voltage level (i.e., the first output signal OUT01 of the signal generator circuit 5), changing from “L” level to “H” level, and the third input signal IN13′, which is a control signal for the high voltage level (i.e., the fourth output signal OUT04 of the signal generator circuit 5) changing from “H” level to “L” level cause both the amplified output signals OUT11, OUT12 to transition to the low voltage “L” level. However, if the second input signal IN12′ transitions to “L” level before the third input signal IN13′ transitions to “H” level in the level shifter 200 having a signal generator circuit, a through current flows between the high voltage power supply Vpp and the ground potential VSSH through the high voltage P-ch transistor P22, high voltage N-ch transistor N21, high voltage P-ch transactor P23, and high voltage N-ch transistor N22.
As mentioned above, the conventional level shifters 100, 200 having a signal generator circuit have a problem that a through current flows between the high voltage power supply Vpp and the ground potential VSSH when the timing at which the output signal at high voltage level of the signal generator circuit 5 changes shifts from the timing at which the output signal at low voltage level changes.
It should be noted that a faint through current merely flows in the respective level shifters 100, 200 having a signal generator circuit. However, since an apparatus typically incorporates an immense number of level shifters 100, 200 having a signal generator circuit, through currents flowing in the overall apparatus sum up to an immense amount. This causes a problem that the through currents break a variety of circuits incorporated in the apparatus. Another problem lies in that an immense amount of power is consumed for nothing.
For example, a source driver for a large TFT display incorporates an immense number of level shifters 100, 200 having a signal generator circuit for controlling (selecting) outputs with a high voltage level. Since the number of level shifters is calculated by the number of gradation bits multiplied by the number of outputs, a large TFT display will include 3312 level shifters when it has eight gradation bits (256 gradation levels) and 414 channels of outputs. Even though a faint amount of through current flows in each of individual level shifters 100, 200 having a signal generator circuit, the through currents flowing in such a number of level shifters 100, 200 having a signal generator circuit will sum up to an immense amount in the overall apparatus. Supposing that a certain circuit incorporated in an apparatus is applied with a through current which exceeds a tolerance of the circuit, the circuit will be broken. In addition, since the through current is a useless current, an immense amount of power is consumed for nothing.